1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and more particularly to an integrated circuit including a phase detector.
2. Description of the Related Art
Generally, a semiconductor device including a DDR SDRAM (Double Data Rate Synchronous DRAM) may receive a clock signal from an external device and may convert the received clock signal into an internal clock signal suitable using a clock generation circuit. The internal clock signal may then be sued by internal circuits to perform a variety of operations. Representative examples of well-known clock generation circuits include a delay locked loop (DLL) clock generation circuit and a phase locked loop (PLL) clock generation circuit.
The PLL and the DLL clock generation circuits may generally have similar configurations and may both include a phase detector. However, PLL clock generation circuits employ a voltage controlled oscillator (VCO) to generate an internal clock signal, whereas DLL clock generation circuits employ a voltage controlled delay line (VCDL).
Recently, semiconductor devices may also include a clock data recovery (CDR) circuit for recovering data and clock signals using data inputted from an external device. Briefly, a CDR circuit may receive high-speed data, detect a clock signal component within the data, recover an internal clock signal from the detected clock signal component, and recover actual data according to the recovered internal clock signal. Existing CDR circuits have a similar configuration to PLL clock generation circuits for recovering a clock signal. Generally, a CDR circuit may recover an internal clock signal and align the phase of the recovered internal clock signal with the center of the data. A phase detector may detect whether the phase of the internal clock signal is aligned with the center of the data. According to the detection result, the phase detector may generate a control signal for performing a phase shifting operation commonly referred to as a down or an up operation depending on whether a phase is advanced or delayed. Conventional phase shifting operations will now be described with reference to FIGS. 1 and 2.
FIG. 1 is a diagram illustrating the operation of a phase detector included in a conventional CDR circuit.
Referring to FIG. 1, three cases are illustrated denoted generally with reference symbols (A), (B) and (C). In case (A) a clock signal CLK may lead the center of data DIN In case B) a dock signal CLK may lag behind the center of the data DIN. In case (C) a dock signal CLK, and a clock bar signal /CLK having a 180 degree phase difference with the clock signal CLK, are phase-shifted through a down operation based on case (A) or an up operation based on case (B).
In case (A), data D1 may be synchronized with a first rising edge of the clock signal CLK and with a rising edge of the clock bar signal /CLK, and data D2 may be synchronized with a second rising edge of the clock signal CLK. For example, the data D1, D1, and D2 may be synchronized in response to the clock signal CLK and the clock bar signal /CLK, and the phase detector may generate a control signal for a down operation. The CDR circuit may perform the down operation to delay the clock signal CLK and the clock bar signal /CLK. Hence the clock signal CLK and the clock bar signal /CLK may have phases as illustrated in case (C).
In case (B), the data D1 may be synchronized with the first rising edge of the clock signal CLK. The data D2 may be synchronized with the rising edge of the clock bar signal /CLK and the second rising edge of the clock signal CLK. For example, the data D1, D2 and D2 may be synchronized in response to the clock signal CLK and the clock bar signal /CLK, and the phase detector may generate a control signal for an up operation. The CDR circuit may perform an up operation to advance the clock signal CLK and the clock bar signal /CLK. Hence, the dock signal CLK and the clock bar signal /CLK may have phases as illustrated in case (C).
In case (C), the rising edge of the clock signal CLK may be positioned at the center of the data DIN, and the rising edge of the clock bar signal /CLK may be positioned at the edge of the data DIN. Thus, when the DIN is sampled by the dock signal CLK, the data may be recovered.
The data DIN may have a phase difference of one half of a cycle T of the clock signal CLK. For example, the phase difference between the data DIN and the clock signal CLK may be ½T.
FIG. 2 is a block diagram illustrating a conventional phase detector for performing the operations of FIG. 1.
Referring to FIG. 2, a conventional phase detector may include first to third synchronization units 210 to 230, a combinational logic unit 240, a decoding unit 250, and a fourth synchronization unit 260.
The first synchronization unit 210 may synchronize the data DIN with the clock signal CLK and output the synchronized data as a first synchronized signal 2NA. The second synchronization unit 220 may synchronize the data DIN with the clock bar signal /CLK and output the synchronized data as a second synchronized signal 2NB. The third synchronization unit 230 may synchronize the first synchronized signal 2NA with the clock signal CLK and output the synchronized signal as a third synchronized signal 2NC.
The combinational logic unit 240 may perform a logical operation on the first synchronized signal 2NA, the second synchronized signal 2NB, and the third synchronized signal 2NC to output first to third logic values LO1 to LO3. An external device, the combinational logic unit 240 may include a plurality of XOR gates XOR. When the first synchronized signal 2NA is replaced with A, the second synchronized signal 2NB is replaced with B, and the third synchronized signal 2NC is replaced with C, the first logic value LO1 may correspond to A XOR C, the second logic value LO2 may correspond to A XOR B and the third logic value LO3 may correspond to B XOR C.
The decoding unit 250 may generate a source signal of an up or down control signal CTR_UD by decoding the first to third logic values LO1 to LO3. For example, we consider a case where the data D1 of the data DIN is logic high, and the data D2 is logic low. Then, the decoding unit 250 may generate the source of the up or down control signal CTR_LID for the up operation when the first and second logic values LO1, LO2 are logic high, and the third logic value LO3 is logic low. The decoding unit 250 may generate the source signal of the up or down control signal CTR_UD for the down operation when the first and third logic values LO1, LO3 are logic high and the second logic value LO2 is logic low.
The fourth synchronization unit 260 may synchronize the output signal of the decoding unit 250 with the clock signal CLK, and output the synchronized signal as the up or down control signal CTR_UD.
The dock signal CLK and the clock bar signal /CLK may be filially shifted to the positions as illustrated in case (C) of FIG. 1, via the up or down operation performed in response to the up or down control signal CTR_UD. Hence, the data DIN may be sampled in response to the shifted clock signal CLK indicating that the clock signal CLK may be used to recover the data DIN. The first synchronized signal 2NA serving as the output signal of the first synchronization unit 210 may correspond to the recovery data.
Generally, conventional CDR circuits employing conventional phase detectors such as the one illustrated in FIG. 2 require a relatively long time to position the rising edge of the clock signal CLK to the center of the data DIN. Hence, improvements are desirable.